FPGA Design Software: An Overview of Time-to-Integration Features in Xilinx’s Vivado Design Suite

This article will look at some of the most important features of the Xilinx Vivado Design Suite which accelerates the "time to integration" of the design procedure.

Traditional FPGA design mainly focuses on the concept of programmable logic and I/O. However, today’s complex applications require going beyond programmable logic to “programmable systems”. This is one of the most fundamental ideas behind the creation of the Xilinx Vivado Design Suite.
Vivado is an IP- and system-centric design environment which attempts to simplify integration of soft IPs. This is achieved through several features that will be briefly discussed in the rest of the article.
Note that the features covered in this article mainly aim to accelerate the “time to integration” of the design process. In another article, we’ll discuss those features of the Vivado that intend to accelerate the “time to implementation” of the design.

Extending the Vivado IP Repository

Vivado has an extensible IP catalog that can include Xilinx and third-party IPs. Vivado enables engineers to quickly turn a part of their design or algorithm into a reusable IP added to the Vivado IP catalog.

As illustrated in Figure 1, with the Vivado IP Packager, all the associated files of the design, such as constraints, test benches and documentation, can be added to the created IP.

Figure 1. Vivado IP creation flow. Image courtesy of Xilinx.

One of the important features of the Vivado IP flow is the ability to create an IP at any level of a design, no matter if it's a Register-Transfer Level (RTL) design, a netlist, a placed netlist, or even a placed-and-routed netlist.

Also note that, as shown in Figure 1, the source files of the IP Packager can include MATLAB/Simulink algorithms from Xilinx System Generator or C/C++/SystemC algorithms from the Vivado High-Level Synthesis (HLS). In these cases, the proprietary IP generation is further accelerated because a higher level of description is utilized to develop the target algorithm. The HLS will be briefly discussed in the next section.

C-Based IP Generation with Vivado HLS

Development of today’s advanced algorithms is not straightforward, even for the most experienced RTL teams. That’s why tools such as Vivado HLS, that can receive C/C++/SystemC algorithms and extract VHDL or Verilog code, can significantly accelerate IP development and, consequently, the design process.

Vivado HLS allows the engineer to explore the design space and find several different implementations for the same source code as shown in Figure 2 below.

Figure 2. Exploring the design space with HLS. Image courtesy of Xilinx.

As you can see, the tool can optimize several design parameters such as area, latency, and throughput.
It's also possible that an engineer may use the HLS to find a solution better than that of the hand-coded RTL. Figure 3 below compares the results of RTL approach with that of HLS for a radar design example.

Figure 3. Comparison of RTL approach with HLS. Image courtesy of Xilinx.

To achieve this, the HLS actually takes into account the properties of the target device such as the available DSP48 slices, memory and SRL blocks. It also tries to efficiently implement the floating-point algorithms and automatically extract parallelism at different levels.

High-level programming languages, such as C, can be extremely helpful in the algorithm verification stage, too. The designer can rapidly model and iterate the design using C functional specifications and then create a target-aware RTL architecture. In a video design example, the C model accelerated algorithm verification time by about 12,000 times. Some details of this experiment are shown in Figure 4 below.

Figure 4. Simulation time for RTL and C models. Image courtesy of Xilinx.

The Vivado HLS design flow is illustrated in Figure 5.

Figure 5. The Vivado HLS design flow. Image courtesy of Xilinx.

High-Level System Integration

Now that we have solutions to rapidly develop the required IPs, it’s reasonable to think about methods of rapidly connecting these IPs to each other. To make this possible, Vivado has the IP Integrator (IPI) which allows the user to graphically describe the connections between the IPs.
A designer can construct the connections at either the interface level or the port level. Choosing to work at the interface level enables the ability to group a large number of individual signals that are used for a common function—and easily manipulate them.

For example, it's possible to use a single connection to connect all the signals of the interface. Alternatively, the design rule checking (DRC) capability of the tool can make sure that the connections of the interface are correct. Hence, the design will be correct-by-construction. Such DRCs on complex interfaces can significantly accelerate the design assembly stage.
In addition to the intelligent auto-connection of key IP interfaces, IPI supports parameter propagation between the connected IPs. The concept of IP parameter propagation is shown in Figure 6.

Figure 6. IP parameter propagation. Image courtesy of Xilinx.

Assume that the data bus width of IP1 has a default value of 32 bits. Now assume that the user connects IP1 to IP0 which has a bus width of 64 bits. In this case, the parameter propagation rules of the tool can detect that the bus width has changed. The user may either allow the IPI to automatically update the bus width of the IPs or direct the program to simply display an error as an alert of the potential issues in a design.

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This article only briefly reviewed some of the FPGA design features of the Vivado Design Suite. If you’re familiar with similar capabilities in other tools, please share your experiences with us in the comments below.