Stencil Design for Exposed-Pad Packages

A properly designed solder stencil helps to ensure successful reflow soldering with IC packages that have an exposed thermal pad.

Exposed-pad packages have become quite common. They carry a variety of abbreviations—e.g., QFN (quad flat no-lead), DFN (dual flat no-lead), MLF (micro leadframe), MLP (micro leadframe package), LLP (leadless leadframe package), LFCSP (leadframe chip scale package). These packages are understandably popular; they are beneficial in terms of form factor (thanks to the low profile and small footprint), electrical performance (i.e., low lead inductance), and thermal performance.
As usual, though, there are also some difficulties. One of these—namely, proper thermal-pad PCB layout—is discussed in a previous technical brief. Another complication is ensuring that the assembly process is not compromised by improper solder-paste techniques.

The solder-paste issue is perhaps most problematic for designers who 1) have limited experience with exposed-pad packages and 2) create a custom PCB footprint, instead of using an existing footprint from a reliable part library. The trouble is, if you use a typical surface-mount pad for the part’s thermal pad, the PCB layout software will treat this pad like any other. This means that the paste-mask layer will have an opening that includes the entire pad (minus the specified paste-mask shrink). Usually this is fine, but with thermal pads, it can be a problem.

The primary concern with a full-pad solder-paste application is “floating”—an excessive amount of solder between the thermal pad and the PCB can cause the entire component to float above the level at which the perimeter lands can make contact with their pads:



Another disadvantage of a full-pad application is related to the chemical changes that occur during the soldering process. As temperature increases, volatile solder-paste compounds vaporize in a process known as outgassing. If these gases cannot escape in an orderly fashion, they can interfere with component placement and lead to unpredictable solder voids.

One thing to keep in mind before we continue is that the size of the exposed pad influences the risk associated with a full-pad solder-paste application—smaller exposed pads are more like normal surface-mount connections, which of course don’t require solder-paste modifications. My guess is that most exposed pads are large enough to warrant special stencil design, but the issue is certainly more pronounced as the size of the exposed pad increases.

The dominant special stencil design is the “window pane” arrangement, also referred to with terms like “pad array,” “cross-hatching,” and “matrix.” This approach allows volatiles to escape without causing mischief and reduces the amount of solder between the PCB and the exposed pad. The following diagram conveys the general idea.



The overall solder coverage (i.e., the ratio of solder area to exposed-pad area, here expressed as a percentage) can be controlled by adjusting the geometry of the matrix—assuming that you know what the overall coverage should be. You’re not likely to figure out the “ideal” ratio, but a review of reliable literature indicates that you should aim for at least 50% and not more than 80%.

In general, the lower percentages are probably preferable simply because they are farther from the risks associated with 100% (i.e., full-pad) coverage. If you’re dealing with high power consumption, you might be inclined to move toward 80% in order to facilitate heat flow from the thermal pad to the PCB; however, this document from Texas Instruments indicates that 50% coverage is adequate even for high-power applications.