Renesas Introduces Security-Focused RA Family of Arm-Based MCUs

The new devices, based on the Arm Cortex-M, bring advanced security to edge devices and IoT endpoints.

The new family of devices deliver a powerful combination of performance, security, and peripheral IP in an open architecture. This enables engineers to reuse legacy code and combine it with software not only from Renesas but also from its expanding partnership ecosystem.

The Renesas RA Family of ARM Cortex-M MCUs. Image used courtesy of BusinessWire

The family includes the RA2 series (speeds up to 60 MHz), the RA4 series (speeds up to 100 MHz), and the RA6 series (speeds up to 200 MHz). The dual-core RA8 will be the next iteration in the family.

“RA MCUs offer customers the ultimate IoT security by combining our secure crypto engine IP with NIST CAVP [Cryptographic Algorithm Validation Program] certifications on top of Arm TrustZone® for Armv8-M, while also providing tamper detection and reinforcing resistance to side-channel attacks,” said Roger Wendelken, Senior Vice President of Renesas’ IoT and Infrastructure Business Unit. “Scalability and compatibility across the RA family let customers build a range of products, and they can quickly begin development with our flexible software package using Amazon FreeRTOS, ThreadX, or other RTOS and middleware solutions.”

RA Family Product Group

Renesas has introduced 32 of these MPUs. They span across five groups within the RA2, RA4, and RA6 series. They feature either Cortex-M4 or Cortex-M23 processor cores with 256 KB to 2 MB of code flash memory and 32 KB to 640 KB of SRAM. The easy-to-use FSP (flexible software package) features Amazon’s FreeRTOS, an open-source OS for edge device MCUs that facilitates connection to the AWS cloud.

RA2 Series 
RA2A1 Group

RA4 Series 
RA4M1 Group

RA6 Series
RA6M1 Group
RA6M2 Group
RA6M3 Group

Comparison across the series and groups within the RA family. Image used courtesy of Renesas

Development kits are available for all of the extant groups of the RA Family, allowing engineers to get products to the market faster.

Security Comes First for the RA Family

At present, the family is all certified to PSA (Platform Security Architecture) Level 1. These first 32 members of the RA family include solid, hardware-based security features, including AES (Advanced Encryption Standard) acceleration and integrated crypto subsystems based within the MCU. Renesas' Secure Crypto Engine, an isolated subsystem of the MCU, provides symmetric and asymmetric encryption and decryption, hash functions, true random number generation (TRNG), and advanced key handling (which includes key generation and key wrapping unique to the MCU).

The Secure Crypto Engine. Image used courtesy of Renesas

 

If the correct access protocol is not followed, an access management circuit shuts down the crypto engine. Dedicated RAM ensures that plaintext keys are never exposed to any CPU or peripheral bus.

Upwards Compatibility and Continued Emphasis on Security

Feature compatibility, and even pin-to-pin compatibility, is an important hallmark for Renesas because it facilitates all transitions within the family.

The RA future will include PSA-certified and Trusted Firmware-M compliant devices. These will include Cortex-M33 MCUs, low-power Cortex-M23 MCUs, and BLE / IEEE 802.15.4 wireless IoT products. These important security measures will enable designers to quickly and confidently deploy both the secured IoT endpoint and edge devices. This level of security for smart factory equipment may form the basis of Industry 4.0.

Around the Industry

Given the popularity of Arm System IP and the burgeoning demand for security at the edge device level, it’s no surprise that Renesas is expanding its family of 32-bit MCUs.
Similar products on the market include Microchip’s SAM L10 and SAM L11 MCU family, which also feature Arm TrustZone technology. The 32-bit devices run at 32 MHz and only require what Microchip claims is the lowest operating power in their class.

ST’s STM32L4S7Z is an MCU based on the Arm Cortex-M4 32-bit RISC core. The unit embeds a HASH hardware accelerator and an AES.