Researchers at IBM Have Prototyped a 3 Bits-Per-Cell PCM

Researchers at IBM’s Zurich laboratory have demonstrated the feasibility of 3 bits-per-cell storage using phase-change memory (PCM) technology under large temperature fluctuations.

The research team, which shared their findings at the International Memory Workshop in Paris, attempts to build a high-speed, non-volatile universal memory technology. Memory with these features has sparked the interest of several groups and been the target of multiple research endeavors. As an example, 3D XPoint is a fast, non-volatile memory chip recently designed by Intel and Micron.

PCM's Potential
General-purpose PCM can be either used in a standalone fashion or paired with a flash memory where the PCM acts as an extremely fast cache. Storing the operating system in PCM, a mobile phone would be able to turn on in a few seconds. Data servers and machine-learning algorithms are other potential applications on which PCM can have a significant impact.
Tripling the amount of data stored in PCM, IBM scientists hope to bring the PCM chips closer in cost to flash memory. PCM is about 100 times faster than flash memory. Unlike a flash USB stick, which endures only 3000 write cycles, the non-volatile PCM is capable of being rewritten by at least 10 million times. With this unique set of properties, PCM can revolutionize the future of memory industry.

The PCM Technology and Multilevel Cell (MLC)

A PCM cell consists of a chalcogenide alloy, typically Ge2Sb2Te5 (GST), which is placed between two metallic electrodes. The structure is capable of changing from a crystalline to an amorphous state and exhibiting different resistivity levels accordingly. The PCM technology uses these resistance levels to represent bits of information.
To read the stored bit back, we can apply a small voltage and measure the cell current. This is how rewritable Blu-ray discs store videos.
One decade of intensive development has brought PCM to an advanced level with many desirable features such as scalability, low write/read latency, and the potential for high capacity.

Figure 1: An array of the PCM cells where each cell consists of a transistor to access the cell and a phase-change storage element. Image courtesy of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Since there is a large resistivity contrast between the resistances of the crystalline state and the amorphous state (typically 3-4 orders of magnitude) and the resistance can vary in an analog manner, it is possible to employ the intermediate resistance levels to store multiple bits of information and achieve an MLC PCM.

MLC (multilevel cell) memory, which is storage of more than one bit of information in a memory cell, was first applied to PCM in 2009. However, MLC PCM threatens the performance reliability, mainly because of phenomena such as resistant drift and cell variability.

Resistance Drift and Cell Variability

Resistance Drift

After you program a PCM cell, its resistivity will monotonically increase with time. There are also some random fluctuations around this monotonic behavior. This steady increase in resistivity, called resistant drift, is attributed to the physical properties of phase-change materials.
Figure 2 shows how the resistance changes after programming a PCM cell. Moreover, this figure shows, that for higher values of the programmed resistance, higher resistance variation is expected.

Figure 2: After programming a PCM cell, the cell resistance increases due to the “resistance drift” phenomenon. Image courtesy of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems

A simple equation to model resistance drift is


is the cell resistance at time
is an arbitrary time,
, and
is the drift exponent. The drift exponent has significant impact on how much the measured parameter (here, resistance
) varies with time.
Due to the resistance drift, we need to choose a considerable margin between resistance levels so that we can have distinguishable levels of resistance to store multiple bits of information.

Cell Variability

Cell variability, another setback to MLC PCM, means that we cannot build cells with 100% relative matching. In other words: During fabrication, the critical dimensions of cells will slightly vary from one cell to another. Therefore, for the same electrical stimuli, different cells might exhibit different resistance levels.

Both of these issues, resistance drift and cell variability, also make the readout of the stored resistance level of a PCM cell challenging.

Figure 3: IBM’s multibit PCM chip connected to a standard integrated circuit board. Image courtesy of

IBM’s Solutions to Build an MLC PCM

To build a practical MLC PCM, IBM proposed to change the readout scheme from R-metric to M-metric and then combined these two metrics to arrive at an enhanced version of M-metric called the eM-metric (or "enhanced metric").

The R-metric, which is the conventional method to measure the resistance of a PCM cell, applies a low voltage to bias the cell and then measures its current. The R-metric is simple and fast—however, it exhibits higher sensitivity to resistance drift and it suffers from low signal-to-noise ratio at higher resistance values. This is due to the fact that the applied voltage is typically small and therefore we need to measure a small current for a high resistance value. Such small currents can be more severely affected by the noise components. As a result, the SNR (signal-to-noise ratio) will reduce.
The M-metric evaluates the cell state by applying a bias current and measuring the voltage developed on the cell. Interestingly, with this choice the sensitivity of the metric to resistance drift will significantly reduce. As shown in Figure 4, the drift exponent of the new metric is almost an order of magnitude smaller than that of the R-metric, which was depicted in Figure 2.

Figure 4: The M-metric exhibits smaller sensitivity to the resistance drift. Image courtesy of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Combining the benefits of the R- and M-metrics, the eM-metric offers improved contrast in reading the state of the cell and provides better SNR in low-resistive states.     

The new readout metrics improve the reliability of MLC PCM storage with respect to drift, noise, and temperature fluctuations. Moreover, the research team has introduced a class of modulation codes which is based on the relative order of resistance levels and not on the absolute value of them. As a result, the technology further improves in reliability and is not affected by the shifts of the levels.
The coding and detection scheme tracks temperature variations within the cell and makes the memory non-volatile. The adaptive scheme modifies the threshold levels, which are used to determine the cell’s stored data in such a way that that the design becomes insensitive to temperature variations.

There is still a great deal of work to do before PCM can replace DRAM or Flash memories. Unlike single-bit PCM, which is almost as fast as DRAM, multi-bit PCM is dramatically slower. Moreover, PCM cannot hold the data as long as Flash memory and its programming consumes a lot of power. However, the discussed research is still a milestone in paving the way to commercializing PCM technology.

For a detailed discussion about the theory and the practical circuit implementations, please read the paper “Multilevel-cell Phase-Change Memory: A Viable Technology”, published recently in the IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
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